← Back to the Chips and hardware tiles
Chip design IP and EDA
14 records Generated from this page's data. Click a name to open its panel on the Chips and hardware page. Records resting on one source are tagged "one source".| Record | What it is | Place | Links | Confidence |
|---|---|---|---|---|
| AIDECompanies | University of Glasgow project building AI tools for electronics engineers; selected for ChipStart UK cohort 3; aimed to launch first products late 2025. pre-incorporation | Glasgow | gla.ac.uk/news/headline_1170712_en.html | one source |
| APRIL (AI for Productive Research & Innovation in eLectronics) hubSchemes, programmes and AI lines | Edinburgh-anchored national hub applying AI to electronics and chip research, linking 20 universities and 30+ industry partners. | Edinburgh | gov.uk/government/publications/semiconductor-sec | one source |
| Arm Flexible AccessSchemes, programmes and AI lines | Arm programme giving start-ups low- or no-cost up-front access to its chip IP; added the Armv9 edge AI platform in October 2025; 300+ members. | Cambridge | newsroom.arm.com/news/arm-flexible-access-armv9- · newsroom.arm.com/blog/arm-embedded-world-2026 | verified |
| Arm Scalable Matrix Extension 2 (SME2)Chips, models and products | Arm CPU architecture extension for matrix maths used to speed up AI in Lumex and the C1 cluster. launched | Cambridge | newsroom.arm.com/blog/top-12-innovations-from-ar | one source |
| FlexcitonCompanies · also on Start-ups | Sells AI and optimisation software that schedules work inside semiconductor factories (description from Package 1, not re-opened). | London (EC2A 3BX) | Companies House · find-and-update.company-information.service.gov. | one source |
| Heronic Technologies (HeronIC)Companies | London start-up making software that designs custom AI accelerator architectures for FPGA chips and an ASIC tool flow; ChipStart UK cohort 2. | London | siliconcatalyst.uk/portfolio-companies · gov.uk/government/news/government-scheme-helps-u | verified |
| Imperas Software (acquired by Synopsys)Companies | Pioneer of RISC-V instruction-set simulators (ISS), virtual prototypes, and processor verification tools used across custom AI accelerator design. | Thame, Oxfordshire | — | one source |
| Moortec Semiconductor (now Synopsys)Companies | World leader in in-chip Process, Voltage, and Temperature (PVT) sensing IP integrated into almost every -edge 3nm/5nm AI GPU and accelerator to prevent thermal throttling. | Plymouth | — | one source |
| Quinas TechnologyCompanies | ULTRARAM compound semiconductor universal memory IP (spun out of Lancaster University by Prof. Manus Hayne). | Lancaster | — | one source |
| SureCoreCompanies | Ultra-low-power embedded SRAM IP, cryogenic memory IP for quantum/AI, and CompuRAM in-memory compute compilers. | Sheffield | — | one source |
| Thalia Design AutomationCompanies | AMALIA EDA automation software for analog, RF, and power management IP node migration. | Cwmbran, South Wales | — | one source |
| UK Chip Design Enablement ProgrammeSchemes, programmes and AI lines | STFC-run pilot programme supporting UK chip design; Southampton's £3m SoC Labs AI chip skills programme works alongside it. pilot | southampton.ac.uk/news/2026/06/southampton-to-he | one source | |
| UltraSoC (now Siemens EDA Embedded Analytics)Companies | Spun out of Cambridge/Essex; provides on-chip hardware telemetry, cybersecurity monitoring, and performance debugging IP embedded inside AI accelerators and automotive SoCs. | Cambridge | — | one source |
| WaveforgeCompanies | Start-up making AI-powered design tools for antennas, analogue and RF circuits; ChipStart UK cohort 3. | siliconcatalyst.uk/portfolio-companies | one source |